3.4.1 Simplified circuit of an Open Collector NAND Gate T3 will therefore be turned off and the external pull up resistor R EXT will pull the collector voltage of T3 up to +V, which will be at the valid logic 1 level of the next gate.įig. 3.4.1, when both inputs A and B are at logic 0, the high voltage applied to T1 base will cause it to turn on, so that T1 collector will go to near 0V and T2 will turn off.Īs T2 is off there will be virtually no current through R3 so the voltage at T3 gate will be around 0V. Instead of the normal Totem Pole output stage, the single output transistor T3 has its collector brought out to an external pin, which can be connected to an external power supply, at a different voltage to the V CC supply of the IC, via an external load resistor R EXT. The grey area illustrates a single gate within an IC. 3.4.1 shows the internal circuit of an open collector NAND gate.
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